The present invention relates to operation of a basic input/output system (BIOS) in a computer environment. More specifically, specific embodiments of the invention enable multi-processing in a BIOS environment.
Most computers, and particularly those based on the conventional PC architecture, employ a BIOS stored in non-volatile memory to load the operating system at boot up, perform a power-on self test, and provide a set of low-level routines that the operating system uses to interface to different hardware devices. For example, as part of the self test, a processor executing the BIOS code typically performs an initialization and test of the system RAM by writing and reading data patterns to and from the system RAM.
Even in multi-processor systems, conventional BIOS code is single-threaded, i.e., only one processor (typically referred to as the boot strap processor or the BSP) operates at any given time. The BSP executes most of the boot code in the BIOS with only brief periods where code may be executed by another secondary processor. During these times, the boot or primary processor remains in a wait state until the secondary processor finishes execution of its code.
The single-threaded nature of conventional BIOS code has increasingly become a bottleneck at boot up as the amount of system memory to be tested has grown. That is, the time required for a single boot processor to fully test system RAM (which might be on the order of tens or hundreds of gigabytes) is becoming undesirably long. One solution could be to test only portions of the system memory. Another is to test the system memory less thoroughly. However, incomplete testing of system RAM is undesirable for obvious reasons.
In addition to the length of time required to fully test system memory, there are often hardware components in multi-processor systems between the boot processor and portions of the memory being tested, the failure of which is likely to be inaccurately reported as a memory failure. Obviously, accurate identification of system failures is highly desirable. And given that these intervening hardware components typically have their own tests, it is also desirable to avoid the redundant albeit indirect testing of these components during memory initialization.
It is therefore desirable to provide techniques for initializing and validating system memory in computer systems which address at least some of the foregoing issues. More generally, it is desirable to provide techniques which ameliorate limitations associated with the single-threaded nature of BIOS code.